Referring to FIG. 1, a diagram of a conventional test environment 10 is shown. The test environment 10 verifies the functionality of a design under test (DUT) 14 using a functional model to generate 12 test vectors, sends the test vectors to the DUT 14 and validates 16 the outputs of the design when stimulated by the test vectors. System Verilog/Property Specification Language assertions are being used for smaller parts of the test vector suites to formally verify the test vectors for functionality while the design is under development. However, the current simulation tools do not take the assertions and testbenches in to account simultaneously when calculating the test vector coverage. Therefore, the number of test vectors that would sufficiently test the design is often much less than the actual number of test vectors in use. As such, many redundant test are performed.
Currently no way exists to simultaneously analyze (i) the test vectors from assertions and (ii) the test vectors from testbenches to calculate the resulting coverage. The two test vector sets are commonly treated independently. Conventional methods of testing the design involve writing exhaustive testbenches and independently writing exhaustive assertions to assure that all parts of the design are tested. The conventional methods are inefficient because the test vectors from assertions and the test vectors from the testbenches are not analyzed simultaneously, which leads to redundancy. Furthermore, the redundant testing causes longer run times and longer turn-around-times for the functional verifications.